FRI-2G.303-1-CCT1-06
A DIDACTIC PIPELINED PROCESSOR
Abstract
The inherent complexity of modern processors presents a number of challenges in the learning and teaching process for both computer engineering students and instructors of computer architecture courses. To facilitate students' understanding of the architectural aspects of computer systems, two complementary approaches are typically combined: the study of real-world processors and the study of simplified processor models. This paper presents the design of a didactic RISC processor that employs a 4-stage instruction execution pipeline. With a focus on educational usability, the instruction set and addressing modes have been deliberately simplified to support clarity and ease of understanding. The processor’s pipelined execution model is described, and the functionality of each pipeline stage is outlined. Additionally, it discusses the techniques used to mitigate data hazards and minimize pipeline stalls, ensuring more efficient instruction flow during execution. The specification, modeling, simulation, and implementation of the processor are carried out using the integrated design environment Xilinx Vivado Design Suite, and the testing is performed on the Basys 3 development board.
Keywords
Computer Architecture, Didactic CPU, FPGA
REFERENCES
- Assumpção, J., Ando, O., de Araújo, H., & Gazziro, M. (2024). An Educational RISC-V- Based 16-Bit Processor. Chips, Volume 3 - Issue 4, December 2024, pp. 395-407.
- Chen, Lin & Ma, Xiao & Ji, Xiang (2023). FPGA-based LoongArch Five-stage Pipeline CPU. Journal of Physics: Conference Series.
- Husainali S., Hitesh N., & Abhishek A. (2016). Design of 32-bit 3-Stage Pipelined Processor based on MIPS in Verilog HDL and Implementation on FPGA Virtex7. International Journal of Applied Information Systems. New York, USA, Volume 10 - No. 9, May 2016, pp. 26-37.
- Navarro-Torrero, P., Martínez-Rodríguez, M. C., Barriga-Barros, Á., & Brox, P. (2024). Full Open-Source Implementation of an Academic RISC-V on FPGA. 2024 XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE), Malaga, Spain, 2024, pp. 1-5. Patterson, D., & Hennessy, J. (2014). Computer Organization and Design, Fifth Edition: The Hardware/Software Interface, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA.